ECC-P
What is ECC-P?
   Differences Between ECC (95s) and ECC-P (85s)
   Requirements to use ECC-P
   Enabling ECC-P
   Performance Degredation
   Trivia
What is EOS (ECC On a SIMM)


What is ECC-P?
   ECC-P support is BIOS code that provides for customer selectable memory error detection . One-bit errors are automatically detected and corrected.  All 2-, and some 3- and 4-bit errors, are detected and the system is halted with the error isolated  to a matched SIMM pair.

Differences Between ECC (95) and ECC-P (85s)
  With ECC-P the detection and correction takes place in the memory controller rather than in the memory SIMM as on the Server 95.  The Server 95 ECC support views memory in 1MB segments and has the ability to deallocate a failing segment.  With the Server 85 ECC-P implementation, the system views memory as matched pairs of SIMMs and, in case of a double bit failure, will deallocate both SIMMs in a matched pair. 
NOTE! Parity and ECC-on-SIMM memory can not be installed within the same system

Requirements to use ECC-P
   You have to use matched pairs of memory SIMMs in order to use ECC-P. On a -xKx or -xNx, you MUST use matched pairs no matter if you use ECC-P or parity. With matched pairs, the ECC support is for the entire amount of supported system memory (256MB max on K and N models, 64MB on X models).  Unmatched SIMMs can be installed in the Server 85-xXx ONLY, however, ECC-P can be turned on for matched pair SIMMs only.  For Model 85-xXx ONLY unmatched SIMMs will be run as normal parity memory if they are installed. 

Enabling ECC-P
   ECC capability can be turned on or off without changing any hardware, memory, switches, or opening the cover; enabled or disabled via menus on the System Partition (Ref Diskette).  You may select memory support from a memory checking method item on the system configuration menu screens.  This option allows the user to choose between ECC-P or normal parity operation.

Performance Degredation
   ECC-P detection and correction takes place in the memory controller rather than in the memory SIMM as on the Base 3 and 4 Processor Complex of the Model 95. If ECC-P is enabled, it will cause up to a 14% performance degradation compared to the more efficient Base 3 and 4 Processor Complex (Model 95) which is only 3%. This performance degradation is only for the memory subsystem, not for the total throughput. (Ed. I have heard a few reports (retorts) that it's a little more noticeable than that...)

Trivia
   64 bit memory transfer (Two Way Banked Memory Interleave) for increased performance (when SIMMs installed in pairs); 32 bits go into the 486 and 32 bits go into memory buffer latch. The 64 bit path uses 8 bit correction information for ECC function.



What is EOS?
   The IBM ECC-on-SIMM Memory Upgrades offer 4MB, 8MB, 16MB and 32MB of error-correcting-code (ECC) memory on a SIMM. This upgrade family -- a plug-compatible, fully retrofittable series of 70ns memory modules --allows you to upgrade a parity system to a fully functional single-error-correct (SEC) ECC system. The ECC function is completely self-contained on the SIMM and provides correction of single-bit errors that occur in each byte of SIMM data. No processor changes are required to receive the enhanced reliability this SIMM family offers. 
   The ECC-on-SIMM Memory Upgrades are organized as x36 bits, support parity, and are packaged on a 72-pin JEDEC (Joint Electronic Device Engineering Council) standard SIMM with gold tabs. The 4MB SIMM has IBM presence detects, while the 8MB (Tall and Wide), 16MB and 32MB SIMMs have industry standard presence detects. 
 
Memory Option
Part #
4MB ECC-on-SIMM
75G6500
 Parity Gold 72-pin
8MB ECC-on-SIMM
75G6501
 Parity Gold 72-pin
 4MB SIMM 70 ns
92G7200
 Parity Gold 72-pin 

 
 

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